1. Field of the Invention
The present invention relates to a digital data transmission system in a communication network in which both a time division multiplex line and packet multiplex line are provided, and more particularly to a transmultiplexer arrangement adapted to interconnect the time division multiplex line and the packet multiplex line.
2. Description of the Prior Art
Conventionally, when providing a time division multiplex line in a packet network, the contents of the time division multiplex line are first demultiplexed to individual channels corresponding to respective terminals so that the channels are connected to line terminators through physically independent individual lines. FIG. 1 shows a block diagram for explaining the manner of providing a time division multiplex line in a conventional system. In FIG. 1, a time division multiplex line 151 of a PCM first-order (primary) group in which the bit rate is 1,544 Mb/s (or 2,048 Mb/s), that is, 64 Kb/s.times.24 (or 64 Kb/s.times.32) forms a transmission path which is divided into multiplex lines 152-1 to 152-l of a PCM zero-order group of 64 Kb/s by means of a 01 multiplexer demultiplexer (01 MUX) 101. In the 64 Kb/s PCM zero-order group, data corresponding to a plurality of terminals are multiplexed in accordance with a multi-frame format pursuant to the CCITT Recommendation X. 50 (6+2 envelope scheme). For example, data of 20 terminals having a bearer rate of 3.2 Kb/s or of 5 terminals having a bearer rate of 12.8 Kb/s are multiplexed in a single 64 Kb/s line. Thus, each of the time division multiplex lines 152-1 to 152-l of the PCM zero-order group is divided into independent terminal lines 153-1-1 to 153-l-m and loaded to corresponding line terminators of a packet exchange 180. By the air of high speed signal control equipment 103 of the packet exchange 180, data on the terminal lines 153 respectively corresponding to the individual terminals is transferred, in the unit of a fixed bit number, via a bus 154 to a main memory 104 for storage therein at positions corresponding to loading positions of the lines. When reception of one frame or one packet from a particular terminal line 153 is completed, a controller 105 is informed of the completion of data reception by means of the high speed signal control equipment 103. The controller 105 then analyzes a header part of the packet stored in the main memory 104 and instructs the high speed signal control equipment 103 to send the header part to a packet multiplex line 155 on a destination path. The thus instructed high speed signal control equipment 103 operates to send the packet in the main memory 104 to a designated packet multiplex line 155 via the bus 154. Conversely, data from the packet multiplex line 155 may be sent to the time division multiplex line 151 via the independent terminal lines by processing reverse to the aforementioned one.
As described above, when supporting the time division multiplex line in the packet network in the conventional system, the multiplex line is demultiplexed to individual channels corresponding to respective terminals and thereafter coupled to the exchange with the result that a number of line terminators of the packet exchange are required, corresponding to the number of the independent line terminators. Consequently, although the packet exchange is featured by efficient exchange of data of terminals having high bit rate and low traffic characteristics, the existing packet exchange which requires the same number of line terminators as the terminals even when the terminals have a low traffic prevents the provision of an economical packet switching system.